In active matrix (hereinafter referred as AM) liquid crystal displays (hereinafter referred as LCD) or Organic light emitting diode (hereinafter refereed as OLED) displays, the scan lines in rows cross the data lines in columns to form an active matrix. In practical circuit driving, a progressive scanning method is usually adopted. As AM OLED shown in FIG. 1, the row-scan driving circuit (not shown) sequentially sends row-scan driving signals (Vseli) for various rows to turn on gating transistors of pixels in rows, the data driving circuit (not shown) transfers the voltage on the data lines (Vdataj) into pixel driving transistors and converts it into current for driving the OLED light emitting display.
Usually, the row-scan driving circuit is implemented by cascaded shift registers, with the output of the shift register of each stage being connected to gate transistors of pixels in rows. A shift register can be classified into a dynamic shift register and a static shift register. The structure of the dynamic shift register is relative simple, and needs less number of thin film transistors (TFT); whereas the power consumption is large and the operating frequency band is limited. In contrast, the static shift register has a wider operating band, consumes lower power, and needs more TFT devices. With the dimension of the display panel increasing, the row-scan driving circuit is usually implemented by using the a-Si or p-Si TFT transistors and is produced on the panel directly, which can reduce the interconnection with the peripheral driving circuit, the dimension and the cost. The row-scan driving circuit as designed based on the panel has no requirements on high speed, but requires compact structure and occupying of a small area, so it is mostly implemented by using dynamic shift registers. In addition, it is complex and costly in the process to realize the conventional shift registers adopting PMOS and NMOS transistors, usually requiring 7˜9 layer mask plates), and there is a large transient current, and thus the panel based design mostly adopts dynamic circuits which utilize only NMOS or only PMOS transistors. Considering the performance of the shift register, it is to consider the factors of supply voltage, power consumption, reliability and area. With the dimension of the panel gradually increasing, power consumption and reliability have become more important indices of performance parameters. Usually, for sake of material and film thick, the threshold voltage Vths (absolute value) of the transistors based on amorphous silicon and low temperature polysilicon process are high, which makes the supply voltage and power consumption of the shift registers high.
In a row-scan driving circuit, an output of a shift register of each stage is connected to an input of a shift register of next stage, and the shift registers of the individual stage are controlled by an external clock signal line. In the shift register of each stage, when evaluating (i.e. setting) the output, a bootstrapping method using a capacitor is often utilized to avoid threshold loss, and a pull-up transistor is often used to carry out the reset of the output (in the case of PMOS). Since the load of the outputs of shift registers of the stages are large (generally tens of pF), the dimension of the TFT of the driving output is designed relatively large. When evaluating or resetting the output, a resetting transistor and an evaluating transistor are prevented from tuning on at the same time to produce a large transient current. This is because it will not only increase power consumption but also cause function failure. Meanwhile, the threshold loss problem should also be considered in resetting. If the threshold voltage Vth (absolute value) is so large that the threshold loss is too large to reset the shift register; furthermore, after the reset is completed, the output of the shift register unit of each row should be maintained stable at least during one field scanning cycle.
Such as in the U.S. Pat. No. 6,845,140 and U.S. Pat. No. 6,690,347, a shift register controlled by double clocks is employed, and the resetting for an output of the shift register requires being triggered by an output of next shift register. This approach adds the load of the output of each shift register, increases complexity of wiring in designing a layout, and causes the row-scan driving signals from two adjacent rows to overlap because of the delay of the output, or causes the row-scanner on the whole panel to work abnormally as defects occur in the shift register of a certain row. A better approach is that the evaluating and resetting time of the output is precisely controlled by an external clock so as to avoid a malfunction.
Such as in the U.S. Pat. No. 7,679,597, the resetting transistor M5 is automatically turned off by utilizing the feedback transistor M4 connected between the output and the gate of the resetting transistor M5 (as shown in FIG. 2). The principle is as follows: when evaluating, the output is at low and M4 is switched on, at this time CK1 is at high, and M5 is switched off, cutting off the direct current path from the supply voltage VDD; when resetting, CK1 is at low, M3 is turned on and M5 is switched on to charge the output. Although this structure is simple, when resetting, M3 and M5 are to be turned on at the same time, thus there are two threshold losses to be added. Such design either guarantees that VDD voltage is high enough, rendering power consumption larger, or only can be used in a low threshold value process. In fact, the simplest design is to directly control N3 node by CK1 such that one threshold loss can be reduced, but the consequence is to make the output floating during a half of a clock cycle, and thus the ability for resisting interferences deteriorates.
In the product of C0240QGL of CMEL (ChiMei EL Corporation), the driving circuit as shown in FIG. 3A is used, and the timing chart thereof is shown in FIG. 3B. This circuit is controlled by two inverted clocks, with a feedback transistor M5 being connected between the output and VDD. Except that there are two threshold losses added when resetting, there occurs a transient direct current path during evaluating. The large absolute value of the threshold voltage will result long period of strong competition between M1 and M2. If the threshold voltage of M5 is small, when M2 pulls down a small voltage, the balance will be broken. In contrast, if the absolute value of the threshold voltage of M5 is very large, M2 has to pull down at least absolute value of one threshold voltage, the balance can be broken, thus the output varying from high to low; during this period, a considerably large current has occurred, the state of the circuit becomes unreliable.
In summary, there is a problem that threshold voltage loss is large during the period of evaluating or resetting in currently existing shift registers. With a manufacturing process for high threshold voltage TFT, it is likely that such shift registers cannot provide the resetting transistors with low gate voltages enough to make the resetting transistors provide currents large enough, so that the shift register cannot be reset, resulting in the circuit failure. Although the supply voltage VDD of the shift register can be increased, this will make the power consumption of the circuit increase.